Integrated circuits (ICs) are enclosed within IC “packages.” The IC packages generally include a housing and external pads, connectors, leads or pins on outside edges or an outside surface of the housing. The external connectors are electrically connected to connection pads on IC dies for transferring electrical signals between the enclosed ICs and external components or devices with which the ICs interact. The IC packages are generally mounted on printed wiring boards (a.k.a. motherboards, printed circuit boards, etc.)
IC package designs differ based on a variety of characteristics, such as size, arrangement of external connectors and materials of construction, among many other characteristics. Each IC package must be appropriate for the enclosed IC, depending on IC characteristics such as die size, number of connection pads and amount of heat generated during operation of the chip, among other characteristics.
When a new IC or new IC package is developed, the package or IC/package combination must undergo testing to qualify the IC package to be used in a wide range of conditions. Additionally, particularly for surface-mounted IC packages, the IC package is tested when mounted on a representative circuit board that physically simulates the types of printed wiring boards on which the IC package may be mounted. Such testing is necessary because the internal and external stresses and strains on a board-mounted IC package are different from a free-standing, or un-mounted, IC package. For example, it is important to determine the reliability of the “attach system” (i.e. solder balls, etc.) to the printed wiring board. Also, the stresses on the IC die mounted within the IC package are different when the IC package is board-mounted compared to when the IC package is free-standing.
Tests that focus on the reliability or function of the connection between the IC package and the printed wiring board are commonly referred to as “second-level” tests. On the other hand, tests that focus on internal portions of the IC package are commonly referred to as “first-level” tests. However, the second-level tests commonly involve a combination of first-level and second-level issues, since the attached printed wiring board can affect the IC die and other internal components of the IC package and the electrical signals applied to the external connectors must pass into the IC package to the IC die and back to the external connectors.
The second-level tests generally involve variations in electrical signal bias, ambient temperature, ambient humidity, etc. One commonly performed second-level IC package test is a thermal cycling test defined by IPC-9701, “Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments,” by IPC—Association Connecting Electronics Industries of Northbrook, Ill. Another type of second-level test is an electrical bias test commonly known as a highly accelerated stress test (HAST).
The IPC-9701 test generally subjects the surface-mounted IC package to thermal cycling conditions while electrical signals are supplied to the IC package. The electrical signals are monitored for failure conditions, such as an unacceptable increase in electrical resistance at any given temperature (e.g. −0° C. to +100° C.), which may occur due to thermal expansion and/or contraction of any portion of the IC package. Manual testing then determines the location of the failure condition. In a more practical and new approach the resistances are monitored at fixed intervals during a test consisting of 3500 cycles of −0° C. to +100° C.
The aforementioned HAST test generally subjects the IC packages to electrical bias testing in a relatively harsh environment (e.g. about 130° C. and about 85% relative humidity) to stress the IC packages to accelerate any potential electrochemical problems. The IC packages are placed in relatively expensive sockets that are mounted on a relatively expensive motherboard, and the populated motherboard is placed in a HAST test chamber. The IC packages are thus stressed in the test chamber for a period of time (e.g. about 100 hours). Then the populated motherboard is removed from the test chamber, and the IC packages are removed from the sockets. The IC packages are then connected to an Automated Test Equipment (ATE) and tested to locate any failure condition(s) that may have been caused by the electrical bias stressing.
An improvement to this test apparatus and method is described in U.S. Pat. 6,597,189, filed Nov. 27, 2002 and issued Jul. 22, 2003 to the same inventor and assigned to the same assignee as the present invention. U.S. Pat. 6,597,189 describes a socketless test apparatus and method using test interposer cards on which the IC packages are mounted and which is an improvement over the socket-based tests. The test interposer cards are appropriate printed wiring boards for testing the IC packages in a board-mounted situation.
However, even with the improved interposer cards described above, one of the main disadvantages of ATE of accelerated reliability stressed packaged devices is that in order to place a test package in an ATE test socket, an ATE clamp is used to hold the test package in place and to make good electrical contact between the packaged and the ATE socket. This total force can exceed 100+ lbs. Should the test package may have a broken electrical connection on the second-level, i.e., between the test package and the test interposer card, then the force applied to the top of the test package may falsely mask the broken electrical connection. This is particularly a concern for the evaluation of second order (Device to Board) connections where the BGA connections are the main focus. The force can also cause device to board warpage, thereby placing undue strain on the connections and consequently causing false opens.
In addition, it would be desirable to perform second level testing of an active device contained in the test package. There is no known current methodology to ATE test second reliability of an active device. All the current tests are performed with a Daisy Chain device. Development of a Daisy Chain die is a costly and timely task.
Accordingly, what is needed is an improved method and system for performing second level testing on integrated circuit packages.